Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Signal

A signal represents an electrical connection, wire or bus. Signals are used for communication between processes.

Syntax

  signal SignalName, ... : DataType [Kind] [:=Expression];

  Kind = {guarded signal, either} register bus
    

Where

package--end entity-is--begin-end architecture-is--begin-end block--begin-end generate--begin-end See Declaration

Rules

A signal can be assigned in more than one process only if it has a resolution function. A guarded signal can have individual drivers disconnected from the resolution function. A register with no drivers connected retains its previous value. The Expression gives the initial value of the signal at time zero.

Things to remember

The initial value only initializes drivers within the scope of the signal declaration, so drivers for the same signal in other architectures are not initialized!

Synthesis

The initial value is ignored for synthesis, so be careful! Resolution functions are generally ignored too. Guarded signals are not synthesizable in general.

Tips

Guarded signals (register and bus) are obscure and are generally to be avoided.

Example

  signal A, B: Std_logic_vector(3 downto 0) := "ZZZZ";
    

See Also

Signal Assignment, Data Type, Disconnect, Block, Shared Variable